Abstract and keywords
Abstract (English):
Two-stage triggers synthesized on CMOS-transistors are given. Triggers are based on a “weak” latch and a symmetrical control circuit. The results of comparing the above triggers for energy efficiency are presented, revealing the advantages of synthesized elements over circuits based on standard logic elements.

Keywords:
D–flip-flop, E-flip-flop, JK-flip-flop, standard logic element, power dissipation, performance of the circuit, energy–topological criterion, the circuit simulation
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References

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